A circuit in an integrated CMOS device for more efficiently handling the flyback voltage of an inductive load by providing an additional bipolar transistor for shunting flyback current to the positive voltage source rather than to ground, the entire circuit being fabricated using a CMOS or a BiMOS process.
It is typical in a CMOS device with an inductive load to connect the inductance between the positive dc voltage source and the drain of an NMOS field effect transistor, FET, and to use the FET to alternately supply or cut off current to the inductance. Further, because the p+ source and drain junction of a PMOS are within an n-well on a p-substrate, there automatically exists a vertical bipolar pnp transistor to the substrate. It is also typical to use this pnp transistor to clamp the inductive flyback voltage. When the FET cuts off, the large flyback voltage generated by the inductance is felt at the emitter of this vertical transistor, and there will be a heavy flow of current from the positive voltage supply through the inductance and through this vertical transistor to the substrate. While this limits the flyback voltage, and thereby serves to prevent damage to the circuit, this process is inefficient since this current represents a loss of power in the device, which leads to higher power consumption and a higher device temperature. A circuit which can be fabricated within the basic CMOS process without any added steps or masks, and which would improve the efficiency of the circuit, is needed.